Accurate Fault Modeling and Fault Simulation of Resistive Bridges

This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We demonstrate that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we show that a zero-ohm bridge fault model can be quite optimistic in terms of coverage of voltage-testable bridging faults. 1 Introduction With the increasing density and complexity of VLSI chips, shorts between normally unconnected nodes are expected to be the main type of manufacturing defect [1]. These shorts can be divided into two kinds: intra-gate shorts between nodes within a logic gate, and inter-gate (or external) shorts between outputs of different logic gates [2][3]. Inter-gate shorts, usually called bridging faults, account for about 90% of all shorts [3][4]. Thus in order to accurately estimate the quality of a chip, it is important to have a fault simulator that can simulate realistic bridging faults. The accuracy of a bridging fault simulator depends on the following factors: • determination of the voltages at the nodes involved in